1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device.
2. Description of the Prior Art
FIG. 1 is a layout view of a semiconductor integrated circuit device. Shown in FIG. 1 are I/O area 1 where an I/O buffer was formed, ROM area 2 where ROM was formed, RAM area 3 where RAM was formed, logic area 4 where a logic circuit was formed, logic element area 5 where a logic element was formed within logic area 4, and power supply/ground wiring area 6 where power supply wiring and ground wiring were formed within logic area 4.
FIG. 6 is a plan view showing the configuration of wiring within the logic area of a conventional semiconductor integrated circuit device, and the figure corresponds to the configuration of xe2x80x9cAxe2x80x9d part in FIG. 1. Shown in FIG. 6 are horizontal power supply wiring 101, vertical power supply wiring 102, horizontal ground wiring 103 disposed in parallel with horizontal power supply wiring 101, vertical ground wiring 104 disposed in parallel with vertical power supply wiring 102, horizontal inter-element wirings 105 used for the connection between logic elements, vertical inter-element wirings 106 used for the connection between logic elements, through holes 107 used for the connection between horizontal power supply wiring 101 and vertical power supply wiring 102, and through holes 108 used for the connection between horizontal ground wiring 103 and vertical ground wiring 104.
The power supply wiring, the ground wiring, and the inter-element wiring are formed of metal such as aluminum or copper, for instance. The power supply wiring and the ground wiring have a width that is larger than the width of the inter-element wiring such that the power supply wiring and the ground wiring have resistance to electromigration.
The power supply wiring, ground wiring, and inter-element wiring are formed by etching and dissolving interlayer insulation film at the position where these wiring are formed, to form holes and then burying metal such as aluminum or copper in the holes. FIG. 7 is a sectional view showing the process of etching and dissolving the interlayer insulation film. The etching of interlayer insulation film 111 proceeds in the order of from FIG. 7A to FIG. 7C. As shown in FIGS. 7A-7C, as the etching of interlayer insulation film 111 proceeds, a foreign substance is deposited on the entrance of hole 112, and thereby the sectional shape of hole 112 becomes trapezoidal. Accordingly, the power supply wiring, ground wiring, and inter-element wiring each have a trapezoidal sectional shape. The wider the width of the wiring is, the wider the taper part of the trapezoid is.
FIG. 8 is a sectional view taken along the VIIIxe2x80x94VIII line of FIG. 6. Shown in the figure are taper parts 102a of vertical power supply wiring 102, taper parts 104a of vertical ground wiring 104, and taper parts 106a of vertical inter-element wirings 106.
Widths a2 of vertical power supply wiring 102 and vertical ground wiring 104 are wider than width b2 of vertical inter-element wiring 106. For instance, width a2 is about 0.41 xcexcm, and width b2 is about 0.22 xcexcm. For this reason, widths c2 of taper part 102a of vertical power supply wiring 102 and of taper part 104a of vertical ground wiring 104 are wider than width d2 of taper part 106a of vertical inter-element wiring 106. Accordingly, intervals f2 between vertical power supply wiring 102 and vertical inter-element wiring 106, and between vertical ground wiring 104 and vertical inter-element wiring 106 are wider than interval g2 between vertical inter-element wirings 106. Moreover, interval e2 between vertical power supply wiring 102 and vertical ground wiring 104 is wider than interval f2. Interval e2 is about 0.5 xcexcm, interval f2 is about 0.4 xcexcm, and interval g2 is about 0.22 xcexcm, for instance. Interval h2 between vertical inter-element wiring 106 that is adjacent to vertical power supply wiring 102 and vertical inter-element wiring 106 that is adjacent to vertical ground wiring 104 is 2*a2+e2+2*f2, and is about 2.12 xcexcm.
The conventional semiconductor integrated circuit device is arranged as mentioned above, the sectional shapes of power supply wiring, ground wiring, and inter-element wiring are trapezoidal, and the widths of the taper parts of a power supply wiring and a ground wiring that each have a wide width are wider than the width of the taper part of an inter-element wiring having a narrow width. For this reason, it is necessary to make the intervals between the inter-element wiring and the power supply wiring, and between the inter-element wiring and the ground wiring wider than the interval between the inter-element wirings. Accordingly, there has been a drawback that the wiring density of the inter-element wirings is low, and simultaneously the element density of the logic elements is low.
The present invention has been accomplished to solve the above-mentioned drawback. An object of the present invention is to provide a semiconductor integrated circuit device in which the intervals between an inter-element wiring and a power supply wiring, and between an inter-element wiring and a ground wiring are narrow, and the element density of logic elements is high.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device including: a power supply wiring divided into a plurality of narrow-width power supply wirings; a ground wiring disposed in parallel with the power supply wiring and divided into a plurality of narrow-width ground wirings; an auxiliary power supply wiring connecting each narrow-width power supply wiring; and an auxiliary ground wiring connecting each narrow-width ground wiring.
Here, a narrow-width power supply wiring and a narrow-width ground wiring may be alternately disposed.